In conventional art, in a computer apparatus in which each OS (there may be one OS or a plurality of OSs) and a hypervisor (the computer apparatus may be configured without a hypervisor) are operating as independent modules, a RAS function for handling a CPU exception is realized by a method such as adding a process for handling a CPU exception to each OS or the hypervisor.
For example, Patent Literature 1 discloses a configuration in which a VM monitor (corresponding to a hypervisor in the present Specification) is provided with means to extract failure information of a process being executed in a virtual computer which experienced a main system failure (corresponding to a CPU exception in the present Specification) from a failure information storage area.
For example, Patent Literature 2 discloses a technique for resolving an exception in a virtual computer on which a hypervisor is employed to operate a plurality of OSs.
Specifically, Patent Literature 2 discloses the technique for resolving an exception by copying to the hypervisor a memory image of the portion of a process being executed by an OS when the exception occurred and emulating a privileged instruction included in the process being executed by the OS when the exception occurred.